A new beam synchronous processing architecture with a fixed frequency processing clock. Application to transient beam loading compensation in the CERN SPS machine

New projects being implemented or planned at CERN, such as the LHC Injectors Upgrade (LIU), High-Luminosity (HL-LHC) Future Circular Collider (FCC), motivate change of several architectural paradigms in Low Level RF systems (LLRF). In upgraded Super Proton Synchrotron (SPS) LLRF, distribution RF, revolution frequency, settings and synchronization timings will rely on a deterministic link, White Rabbit (WR), exploiting distributed topology. The digital electronics (FPGA) now use fixed frequency clock extracted locally each node from this data stream. paper presents new solution for algorithms that treat beam-induced perturbations they must solve challenge to tune their processing instantaneous Beam Synchronous Processing (BSP). We dynamic resampling uniform sampled tuning element between sweeping spectrum static with clocks. applies novel method transient beam loading compensation. It One Turn delay FeedBack (OTFB) SPS based cascade two variable ratio resamplers.